Voltage supply circuit

ABSTRACT

A voltage supply circuit capable of starting up a system while maintaining symmetry of a high level selection signal V H  and a low level selection signal V L , not requiring a multistage charge pump circuit, and capable of reducing the number of parts of the system, wherein generation circuits of V D  and V H  are comprised of chopper type booster type switching regulators, and switching timings of a V H  generation circuit  12  and a V L  generation circuit  13  are controlled so that a virtual reference voltage V S  (V D /2) and a middle point potential between V H  and V L  become the same.

TECHNICAL FIELD

The present invention relates to a voltage supply circuit used as apower supply circuit of for example a liquid crystal display device (LCDpanel).

BACKGROUND ART

For example, as a voltage for driving a LCD panel employing the thinfilm diode (referred to as MIM), three levels, that is, a signalelectrode drive voltage V_(D), a high level selection voltage V_(H), anda low level selection voltage V_(L) become necessary.

At this time, the signal electrode drive voltage VD, high levelselection voltage V_(H), and the low level selection voltage V_(L) mustsatisfy the following conditions when a virtual selection voltage isV_(SEL):

V _(L) =−V _(SEL)

V _(H) =V _(D) +V _(SEL)  (1)

Conventionally, in order to obtain these signal electrode drive voltageV_(D), high level selection voltage V_(H), and low level selectionvoltage V_(L), a so-called charge pump type voltage generation circuithas been used.

In a voltage supply circuit generating the above three voltages by avoltage generation circuit of the charge pump type, however, there wereproblems in that equation (1) could not be satisfied with a sufficientprecision (particularly when turning on the power) and in that thenumber of parts of the circuit was too large due to the wide variablerange of the virtual selection voltage V_(SEL) (generally about 2 V to20 V).

DISCLOSURE OF THE INVENTION

The present invention was made in consideration with such a circumstanceand has as an object thereof to provide a voltage supply circuit capableof starting up a system while holding symmetry of the high levelselection voltage and the low level selection voltage and capable ofdecreasing the number of parts of the system without the need of amultistage charge pump circuit.

To attain the above object, a voltage supply circuit of the presentinvention comprises a first voltage generation circuit including achopper type switching regulator for comparing a first reference voltageand an output feedback voltage and generating a first output voltage, asecond voltage generation circuit including a chopper type switchingregulator for generating a second output voltage, a third voltagegeneration circuit including a charge pump for generating a third outputvoltage in accordance with the second output voltage, a virtualreference voltage generation circuit for generating a virtual referencevoltage corresponding to the first output voltage, an intermediatevoltage generation circuit for generating an intermediate voltagebetween the second output voltage and the third output voltage, acomparator for comparing!the virtual reference voltage and theintermediate voltage and outputting an error signal in accordance withthe comparison result, and a control circuit for receiving as input theerror signal and controlling operations of the second voltage generationcircuit and the third voltage generation circuit so that the virtualreference voltage and the intermediate voltage become equal.

Also, in the present invention, the control circuit makes the thirdvoltage generation circuit operate when a voltage difference between thevirtual reference voltage and the second output voltage is larger thanthe voltage difference between the virtual reference voltage and thethird output voltage and makes the second voltage generation circuitoperate when the voltage difference between the virtual referencevoltage and the second output voltage is smaller than the voltagedifference between the virtual reference voltage and the third outputvoltage.

Also, in the present invention, the virtual reference voltage is amiddle point potential between the first output voltage and a groundpotential, and the intermediate potential is the middle point potentialbetween the second output voltage and the third output voltage.

Further, in the present invention, the second output voltage is higherthan the third output voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view of the configuration of a first embodiment of a voltagesupply circuit according to the present invention.

FIG. 2 is a circuit diagram of a concrete example of the configurationof a signal electrode drive voltage generation circuit according to thepresent invention.

FIG. 3 is a circuit diagram of a concrete example of the configurationof a high level selection voltage generation circuit according to thepresent invention.

FIG. 4 is a circuit diagram of a concrete example of the configurationof a low level selection voltage generation circuit according to thepresent invention.

FIG. 5 is a flowchart for explaining an operation at the time of startupof the voltage supply circuit according to the present invention,

FIG. 6 is a flowchart for explaining an operation in a normal mode ofthe voltage supply circuit according to the present invention.

FIG. 7 is a view of the configuration of a second embodiment of thevoltage supply circuit according to the present invention.

FIG. 8 is a view of the configuration of a third embodiment of thevoltage supply circuit according to the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Preferred embodiments of the present invention will be explained belowby referring to the attached drawings.

First Embodiment

FIG. 1 is a view of the configuration of a first embodiment of a voltagesupply circuit according to the present invention.

A voltage supply circuit 10 of the present invention comprises, as shownin FIG. 1, a drive voltage generation circuit 11, high level selectionvoltage generation circuit 12, low level selection voltage generationcircuit 13, error comparator 14, timing control circuit 15, andresistance elements R11 to R18 as principal components.

Further, a middle point voltage generation circuit 16 for generating amiddle point voltage (V_(MHL)) between the high level selection voltageV_(H) as the second voltage and the low level selection voltage V_(L) asthe third voltage is comprised by the resistance elements R13 and R14,while a virtual reference voltage generation circuit 17 for generating avirtual reference voltage V_(MD) as an intermediate potential betweenthe signal electrode drive voltage V_(D), and the ground potential (GND)is comprised by the resistance elements R15 and R16.

The drive voltage generation circuit 11 has a chopper type booster typeswitching regulator as its principal component, compares voltagesobtained by dividing the signal electrode drive voltage V_(D) of theoutput first voltage by the resistance elements R11 and R12 with a firstreference voltage V_(ref1), controls the divided voltages to becomeequal to the first reference voltage V_(ref1), and supplies theoutput-drive voltage V_(D) from an output terminal T_(VD) to a notillustrated load side.

Namely, the output drive voltage V_(D) becomes as follows:

V _(D)=(1+RV11/RV12) V_(ref1)  (2)

Here, RV11 indicates a resistance value of the resistance element R11,while RV12 indicates the resistance value of the resistance:element R12.

FIG. 2 is a circuit diagram of a concrete example of the configurationof the drive voltage generation circuit 11 according to the presentinvention.

This drive voltage generation circuit 11 has, as shown in FIG. 2, adrive voltage selection circuit (V_(D)SEL) 111 built in an IC, analogswitches SW111 to SW114, drive voltage feedback use resistance elementsR111 and R112, a p-channel MOS (PMOS) transistor PT111,error/rectification timing comparator 112, timing control circuit 113,switching use n-channel MOS (NMOS) transistor NT111, synchronizedrectification use PMOS transistor PT112, externally attached inductorL111, rectification use Schottky diode D111 and smoothing capacitor C111as principal components. Note that, in the drive voltage generationcircuit 11 shown in FIG. 2, the resistance elements R11 and R12 shown inFIG. 1 are fetched into an internal portion thereof to obtain theresistance elements R11 and R112.

When an enable signal VDEN is at an active high level, an invertedsignal XVDEN of the enable signal VDEN supplied to the gate of the PMOStransistor PT111 is at the low level, so the PMOS transistor PT111 isheld in a conductive state and a feedback system is established.

Also, while the drive voltage generation circuit 11 is stopped, theswitching use transistor is held in a stopped state. Also, all circuitsincluding the feedback system are stopped in order to minimize theconsumed current.

Note that, the drive voltage selection circuit 111 selects a suitabledrive voltage feedback resistance value from the states of the drivevoltage selection signals VSEL 1 to VSEL 3, sets the resistance elementR112 at an intended value, and controls the drive voltage V_(D).

In the drive voltage generation circuit 11 having such a configuration,first the error/rectification timing comparator 112 acts as an errorcomparator and monitors the drive voltage V_(D). At this time, theanalog switches SW111 and SW112 are held in the conductive state, andthe analog switches SW113 and SW114 are held in the nonconductive stateby the timing control circuit 113.

In this state, when the voltages obtained by dividing the output drivevoltage V_(D) by the resistance elements R111 and R112 become lower thanthe first reference voltage V_(ref1), the error signal is output fromthe error comparator 112 to the timing control circuit 113. The timingcontrol circuit 113 receiving the error signal turns on the output NMOStransistor NT111 for a constant time.

During this time, the error/rectification timing comparator 112 isswitched from a function as an error comparator to a function as arectification timing comparator. At this time, the analog switches SW111and SW112 are held in the nonconductive state and the analog switchesSW113 and SW114 are held in the conductive state by the timing controlcircuit 113.

While the NMOS transistor NT11 is ON, the energy stored in theexternally attached inductor L111 is supplied to the load side throughthe rectification use PMOS transistor PT112 and the diode D111simultaneously with the NMOS transistor NT111 turning off.

The ON/OFF timing of this rectification use PMOS transistor PT112 iscontrolled by the error/rectification timing comparator 112 and thetiming control circuit 113.

When this cycle is completed, the error/rectification timing comparator112 is switched from a function as a rectification timing comparator toa function as an error comparator.

The high level selection voltage generation circuit 12 has a choppertype booster type switching regulator as a principal component,generates the high level selection voltage V_(H), as the second voltagebased on a timing control signal S15 a from the timing control circuit15, supplies the same from an output terminal T_(VH) to the notillustrated load side, and supplies the same to the low level selectionvoltage generation. circuit 113.

Concretely, the high level selection voltage generation circuit 12 iscontrolled by the timing control signal S15 a so that the followingrelationship is held:

|V _(H) −V _(D)/2 |=|V _(D)/2 −V _(L) |  (3)

The low level selection voltage generation circuit 13 has a charge pumpcircuit as a principal component, generates the inverted voltage of thehigh level selection voltage V_(H) based on the high level selectionvoltage V_(H) supplied from the high level selection voltage generationcircuit 12, the voltages obtained by dividing a second reference voltageV_(ref2) by the resistance elements R17 and R18 and a timing controlsignal S15 b by the timing control circuit 15, and supplies thisinverted voltage as the low level selection voltage V_(L) from an outputterminal T_(VL) to the not illustrated load side.

The error comparator 14 compares the virtual reference voltage V_(MD)generated at the virtual reference voltage generation circuit 17 and themiddle point voltage V_(MHL) generated at the middle point voltagegeneration circuit 16 and outputs the result of the comparison as anerror signal S14 to the timing control circuit 15.

The timing control circuit 15 outputs the timing control signal S15 a tothe high level selection voltage generation circuit 12 and outputs thetiming control signal S15 b to the low level selection voltagegeneration circuit 13 in order to control the switching timings of thehigh level selection voltage generation circuit 12 and the low levelselection voltage generation circuit 13 based on the error signal S14 bythe error comparator 14.

Concretely, the timing control circuit 15 controls the switching timingsof the high level selection voltage generation circuit 12 and the lowlevel selection voltage circuit 13 so that the following equation isalways satisfied so that V_(D/)2 and (V_(H)+V_(L) )/2 become identical:

V _(L) =−V _(SEL) , V _(H) =V _(D) +V _(SEL) →V _(H) +V _(L) =V _(D)→(V_(H) +V _(L) )/2=V _(D)/2  (4)

Namely, the timing control circuit 15 performs control so that the lowlevel selection voltage circuit 13 performs a switching operation whenV. is too high, that is, when V_(MHL)((V_(H)+V_(L))/2)>V_(MD)(V_(D)/2),while the high level selection voltage generation circuit 12 performs aswitching operation when V_(L) is too low,; that is, whenV_(MHL)<V_(MD.)

Note that, in the first embodiment of the present invention, theprincipal portion of the high level selection voltage generation circuit12 is built in the same block as that for the error comparator 14,timing control circuit 15, middle point voltage generation circuit 16,and virtual reference voltage generation circuit 17.

FIG. 3 is a circuit diagram of a concrete example of the configurationof the high level selection voltage generation circuit 12.

The high level selection voltage generation circuit 12 has a switchinguse NMOS transistor NT121 built in the IC and an externally attachedinductor L121, a rectification use Schottky diode D122, and a smoothingcapacitor C121 as the principal components as shown in FIG. 3. Also, inthis circuit, a PMOS transistor PT121, wherein a gate is connected to aninput line of the active enable signal VHEN where the active level is ata low level, is connected between a supply line of the drive voltageV_(D) to the virtual reference voltage generation circuit 17 and theresistance element R15 of the circuit 17.

In this high level selection voltage generation circuit 12, theoperation of the circuit is controlled by the enable signal VHEN basedon the entire enable signals etc.

Also, while the drive voltage generation circuit 11 is stopped, theoutput NMOS transistor NT121 is held in the stopped (nonconductive)state.: Also, in order to minimize the consumed current, all circuitsexcept the feedback resistors (R13, R14) are stopped.

The high level selection voltage generation circuit 12 having such aconfiguration operates so that the output voltage V_(H) becomessymmetric with the low level selection voltage V_(L) withV_(D)/2(V_(MD)) as the virtual reference voltage.

When the voltage obtained by dividing the output voltage V_(H) by theresistance elements R13 and R14 becomes lower than the virtual referencevoltage V_(MD), the error signal S14 is output from the error comparator14 to the timing control circuit 15. The timing control circuit 15receiving the error signal S14 turns on the output NMOS transistor NT121for a constant time.

While the NMOS transistor NT121 is ON, the energy stored in theexternally attached inductor L121 is supplied through the rectificationuse diode D122 to the load side simultaneously with the turning off ofthe NMOS transistor NT121.

Also, in the high level selection voltage generation circuit 12, theswitching is automatically controlled so that the symmetry between thelow level selection voltage V_(L) and the high level selection voltageV_(H) with respect to V_(D)/2(V_(MD)) is held when the power is turnedon.

FIG. 4 is a circuit diagram of a concrete example of the configurationof the low level selection voltage generation circuit.

This low level selection voltage generation circuit 13 has, as shown inFIG. 4, low level selection voltage feedback use resistance elementsR131 (R17) and R132 (R18), PMOS transistor PT131, analog switches SW131to SW134, error comparator 131, timing control circuit 132, switchinguse NMOS transistor NT131 and PMOS transistor PT132, start-up controlcircuit 133 and an externally attached capacitor C131, clampuse/rectification use Schottky diodes D131 and D132, and a smoothingcapacitor C132 built in the IC as the principal components.

In this low level selection voltage generation circuit 13, usually thecharge use PMOS transistor PT132 is turned on, and the externallyattached capacitor C131 is charged to the V_(H) potential.

When the low level selection voltage V_(L) becomes higher than the setvalue, an error signal is output from the error comparator 131 to thetiming control circuit 132. The timing control circuit 132 receiving theerror signal turns off the PMOS transistor PT132, turns on the punchdownuse NMOS transistor NT131 for a constant time, punches down the minusside of the bucket capacitor C131, and supplies a charge to a terminalVL side through the rectification use diode D132.

As the reference voltage for generating the low level selection voltageV_(L), use is made of a second reference voltage V_(ref2) (for example 2V) and a voltage VEV set for the start-up.

When the low level selection voltage V_(L) reaches for example −1.6 V,the start-up control circuit 133 receiving the error signal from theerror comparator 131 switches the reference voltage to VSREF and GND. Atthis time, the analog switches SW132 and SW134 are held in theconductive state, while the analog switches SW131 and SW133 are held inthe nonconductive state.

Also, the start-up control circuit according to the present embodimentsimultaneously outputs operation start signals to the drive voltagegeneration circuit 11 and the high level selection voltage generationcircuit 12.

Next, an explanation will be made of the operation by the aboveconfiguration with relation to the timing charts of FIG. 5 and FIG. 6.

FIG. 5 is a timing chart at the time of startup, while FIG. 6 is atiming chart at the time of steady operation.

In the low level selection voltage generation circuit 13, after thestart of the operation, when the low level selection voltage V_(L)reaches a predetermined voltage (−1.6 V in the present embodiment), theerror signal from the error comparator 131 is output to the start-upcontrol circuit 133.

At the start-up control circuit 133 receiving the error signal, thereference voltage is switched to VSREF and GND, and the original lowlevel selection voltage V_(L) is generated. Also, at this time, theoperation start signals are simultaneously output-from the start-upcontrol circuit 133 to the drive voltage generation circuit 11 and thehigh level selection voltage generation circuit 12. Due to this, thedrive voltage generation circuit 11 and the high level selection voltagegeneration circuit 12 enter the operation state.

Then, thereafter, the high level selection voltage V_(H) and the lowlevel selection voltage V_(L) start up so as to become symmetrical aboutV_(D)/2.

In the drive voltage generation circuit 11, the divided voltagesobtained by dividing the output voltage V_(D) by the resistance elementsR111 and R112 are compared with the first reference voltage V_(ref1),and the chopper type booster type switching regulator is controlled sothat the divided voltages become equal to the first reference voltageV_(ref1).

The drive voltage V_(D) controlled in this way is supplied to a notillustrated for example drive system of LCD panel and supplied to thevirtual reference voltage generation circuit 17.

In the virtual reference voltage generation circuit 17, the drivevoltage V_(D) is divided by the resistance elements R15 and R16 andoutput as the virtual reference voltage V_(MD) of V_(D)/2 to the errorcomparator 14.

In the error comparator 14, magnitudes of the supplied virtual referencevoltage V_(MD) (=V_(D)/2) and the middle point voltage V_(MHL) betweenthe high level selection voltage V_(H) and the low level selectionvoltage V_(L) generated at the middle point voltage generation circuit16 are compared. The result thereof is output as the error signal S14 tothe timing control circuit 15.

In the timing control circuit 15, the timing control signals S15 a andS15 b are output to the high level selection voltage generation circuit12 and the low level selection voltage generation circuit 13 in order tocontrol the timings of switching of the high level selection voltagegeneration circuit 12 and the low level selection voltage generationcircuit 13 based on the error signal S14.

More concretely, the timing control circuit 15 controls the timings ofswitching of the high level selection voltage generation circuit 12 andthe low level selection voltage generation circuit 13 so that V_(D)/2and (V_(H)+V_(L))/2 (=V_(MHL)) become identical.

Then, at the time of startup, the low level selection voltage generationcircuit 13 tries to continue the switching until the value of ‘V_(L)Error Input’ (output voltage value) matches the reference voltageV_(REF) as shown in FIG. 5(D), but when (V_(H)+V_(L))/2 (=V_(MHL)) islower than V_(D)/2, it is controlled so as to stop until (V_(H)+V_(L))/2 (=V_(MHL)) becomes V_(D)/2 or more.

Also, at the time of startup, the high level selection voltagegeneration circuit 12 is controlled so as to perform the switching when(V_(H)+V_(L))/2 is lower than V_(D)/2.

Then, even in the steady state, the low level selection voltagegeneration circuit 13 is controlled by the timing control circuit 15 sothat the value of ‘V_(L) Error Input’ of feedback matches with the valueof V_(REF) (=GND) as shown in FIG. 6(D) and performs the switching whenV_(REF) (=GND)<V_(L) Error Input.

Also the on time of the punchdown use NMOS transistor NT131 at this timeis controlled by the internal time constant circuit. Also, when the NMOStransistor NT131 is off, the PMOS transistor PT132 is always held in theon state. Due to this, the capacitor C131 is charged.

The low level selection voltage V_(L) generated in this way is output tothe not illustrated drive system of the LCD panel.

Also, the high level selection voltage generation circuit 12 iscontrolled by the timing control circuit 15 so as to perform theswitching when (V_(H)+V_(L))/2 is lower than V_(D)/2 in the same way asthe time of startup.

The NMOS transistor NT121 comprising the chopper type booster typeswitching regulator at this time is held in the on state for exactly aconstant time controlled by the internal time constant circuit. Further,the off time is similarly controlled so as to reliably perform therectification.

Also, when the NMOS transistor NT131 is off, the PMOS transistor PT132is always held in the on state. Due to this, the capacitor C131 ischarged.

Note, the PMOS transistor PT132 and the NMOS transistor NT131 arecontrolled in their timings of switching by the timing control circuit132 so that they do not simultaneously turn on.

The high level selection voltage V_(H) created in this way is suppliedto the not illustrated drive system of the LCD panel.

As explained above, according to the first embodiment of the presentinvention, the generation circuit of the drive voltage V_(D) and thehigh level selection voltage V_(H) among the three levels required forthe LCD panel drive in the DTFD (MIM) system is comprised of the choppertype booster type switching regulator, feedback is applied so that thevirtual reference voltage V_(MD)(:V_(D)/2) obtained by dividing thedrive voltage V_(D) by the resistor and the middle point potentialbetween the high level selection voltage V_(H) and the low levelselection voltage V_(L) become the same, and the switching timings ofthe high level selection voltage generation circuit 12 and the low levelselection voltage generation circuit 13 are controlled, therefore amultistage charge pump circuit for dealing with a wide range of thevirtual voltage V_(S) is unnecessary, and thus the number of componentsof the system can be decreased.

Also, the system can be started up while maintaining the symmetrybetween the high level selection voltage V_(H) and the low levelselection voltage V_(L). For example, it is possible to preventdeterioration of the characteristics of the liquid crystal due to forexample DC bias.

Second Embodiment

FIG. 7 is a circuit diagram of a second embodiment of the voltage supplycircuit according to the present invention.

The difference of the second embodiment of the present invention fromthe first embodiment resides in the fact that an error comparator 14Aand a timing control circuit 15A are built in the same block as that ofthe principal components of a low level selection voltage generationcircuit 13A in place of a high level selection voltage generationcircuit 12A.

Then, in the second embodiment of the present invention, the high levelselection voltage generation circuit 12A compares the voltages obtainedby dividing the high level selection voltage V_(H) of the output by theresistance elements R19 and R20 with the second reference voltageV_(ref2), and controls the divided voltages to become equal to thesecond reference voltage V_(ref2).

The rest of the configuration: is similar to that of the firstembodiment mentioned above.

According to the second embodiment of the present invention, a similareffect to that by the first embodiment can be obtained.

Third Embodiment

FIG. 8 is a view of the configuration of a third embodiment of thevoltage supply circuit according to the present invention.

The difference of the embodiment of the present invention from thesecond embodiment resides in the fact that a high level selectionvoltage generation circuit 12B is comprised of the charge pump circuitand that the low level selection voltage generation circuit 13B iscomprised by the chopper type booster type switching regulator (Sw,Reg).

The rest of the configuration is similar to that of the secondembodiment.

In the third embodiment of the present invention as will, a similareffect to that by the first embodiment can be obtained.

Also, in the embodiment shown in FIG. 1, it is also possible to make thehigh level selection voltage generation circuit 12 a charge pump andmake the low level selection voltage generation circuit 13 a choppertype regulator. Further, it is also possible to make the drive voltagegeneration circuit 11 a charge pump.

INDUSTRIAL APPLICABILITY

As explained above, according to the voltage supply circuit of thepresent invention, there is an advantage in that a multistage chargepump circuit for dealing with the wide range of the virtual selectionvoltage is unnecessary, so the number of the components of the systemcan be decreased.

Also, startup and driving of the system while maintaining the symmetryof the high level selection voltage and the low level selection voltageare possible and in turn deterioration of the characteristics of theliquid crystal due to for example DC bias can be prevented.

What is claimed is:
 1. A voltage supply circuit comprising: a firstvoltage generation circuit including a chopper type switching regulatorfor comparing a first reference voltage and an output feedback voltageand generating a first output voltage, a second voltage generationcircuit including a chopper type switching regulator for generating asecond output voltage, a third voltage generation circuit including acharge pump for generating a third output voltage in accordance withsaid second output voltage, a virtual reference voltage generationcircuit for generating a virtual reference voltage corresponding to saidfirst output voltage, an intermediate voltage generation circuit forgenerating an intermediate voltage between said second output voltageand said third output voltage, a comparator for comparing said virtualreference voltage and said intermediate voltage and outputting an errorsignal in accordance with the comparison result, and a control circuitfor receiving as input said error signal and controlling operations ofsaid second voltage generation circuit and said third voltage generationcircuit so that said virtual reference voltage and said intermediatevoltage become equal.
 2. A voltage supply circuit as set forth in claim1, wherein said control circuit makes said third voltage generationcircuit operate when a voltage difference between said virtual referencevoltage and said second output voltage is larger than the voltagedifference between said virtual reference voltage and said third outputvoltage and makes said second voltage generation circuit operate whenthe voltage difference between said virtual reference voltage and saidsecond output voltage is smaller than the voltage difference betweensaid virtual reference voltage and said third output voltage.
 3. Avoltage supply circuit as set forth in claim 1 or 2, wherein saidvirtual reference voltage is a middle point potential between said firstoutput voltage and a ground potential, and said intermediate potentialis the middle point potential between said second output voltage andsaid third output voltage.
 4. A voltage supply circuit as set forth inclaim 2, wherein said second output voltage is higher than said thirdoutput voltage.